Physical Design and Simulation of an n stage Ring Oscillator using , 300 nm Technology

Voltage controlled Oscillators or Ring Oscillators are crucial components in any timing and memory circuits. The goal of this paper is to do physical design for a high speed, low power consumption multistage high performance ring oscillator circuit based on 300 nm CMOS technology which provides frequency of high order (KHz). This oscillator is used for high speed wireless communication applications and in control circuitries of numerous analog and digital integrated circuits. This ring oscillator is designed to be controlled in a oscillation frequency by a voltage input. The physical design will include C5 process, simultaneously various design rule check and network consistency checks were performed to improve performance characteristics of the oscillator. The Complementary-Metal-Oxide-Semiconductor (CMOS) is the most popular technology for the modern integrated circuit design and fabrication. Based on this technology, a VCO can be implemented by the LC resonant or Ring structure. In this paper a ring based VCO is design which has small chip area, low power consumption which is suitable for wide tuning band VCO of namely 11 stages, 21 stages and 51 stages. The paper will also focus on various design considerations namely basic cell design, bias circuitry and design implementation and testing of the same.